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一種用于功能磁共振的同步器

A synchronizer used for fMRI

作者: 眭建鋒  梁振  胡孝朋  周小強  何珊  陳月明  何文勝                          
單位:                                 安徽醫(yī)科大學生命科學學院生物醫(yī)學工程系(合肥230032)            
關鍵詞:                               功能磁共振;同步;復雜可編程邏輯器件;兼容性              
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出版年·卷·期(頁碼):2014·33·4(393-396)
摘要:

目的 功能磁共振(functional magnetic resonance imaging, fMRI)在采集圖像數(shù)據(jù)時,有兩種同步信號輸出方式:其一,每采集一層圖像輸出一個同步信號;其二,采集一幅腦圖輸出一個同步信號。由于第一種輸出方式中同步信號過于密集,導致刺激計算機無法及時記錄同步信號,從而失去同步。為此本文設計出一種基于復雜可編程邏輯器件(complex programmable logic devices, CPLD)的單參數(shù)(同步參數(shù))同步器。方法 采集一幅腦圖時,該同步器對第一種同步信號的上升沿進行計數(shù),計數(shù)期間輸出維持高電平,直到最后一個同步信號到來,才把輸出拉低為低電平,從而實現(xiàn)第一種同步信號到第二種同步信號的轉換。然后用Quartus 9.1對信號轉換進行仿真以驗證其功能。結果 經(jīng)過CPLD處理器后,第一種同步信號被處理成第二種同步信號。此外,基于本設計做出的同步器亦成功應用于GE Sigma 3.0T。結論 本文設計了具有同步信號轉換能力的同步器,成功實現(xiàn)了輸出方式的轉變。該同步器達到同步信號轉換要求,并具有較好的兼容性。

Objective Synchronization signal has two output types in the acquisition of the image data by functional magnetic resonance imaging (fMRI). One type is that a synchronization signal is outputted after acquiring each layer image. The other type is that a synchronization signal is outputted after acquiring a whole brain map. However, for the first type of synchronization signal, there is a loss of synchronization because the synchronization signal is too dense to be recorded in time by the stimuli-controlled computer. Therefore, in this paper a single parameter (synchronous parameter) synchronizer is designed based on CPLD. Methods The synchronizer counts the positive edge of the first type of synchronization signal in the acquisition of a brain map. Meanwhile, the output of the synchronizer remains high level and will not be pulled down to low level during the counting period until the last synchronization signal is coming. The synchronizer achieves the translation of the synchronous signal from the first type into the second type. Then we simulate the signal conversion by Quartus 9.1 to verify its functionality. Results The first synchronization signal is processed into the second synchronization signal through the CPLD processor. In addition, the synchronizer based on this design is also successfully applied to GE Sigma 3.0T. Conclusions This research designs a synchronizer which has conversion capability for synchronization signals and successfully achieves the transformation output type. The synchronizer reaches the synchronization requirements with better compatibility.

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